IBM’s New z17 – Do More at the Core – Part 2

In this blog, we further analyze the Redbooks concerning the IBM z17 mainframe computer, focusing on its connectivity, clustering capabilities, processing power, and memory. It explains the “n minus 2” rule for compatibility within a parallel sysplex environment, allowing the z17 to work with z16 and z15 systems. The discussion covers various coupling technologies for both short- and long-distance connections between mainframes, highlighting the use of dense wavelength division multiplexing (DWDM) for extended ranges. Furthermore, the presentation details the z17’s architecture, emphasizing the IBM Telum 2 processor with its high core count, substantial cache hierarchy, and impressive transistor density, alongside the system’s expansive main memory capacity.

Here are the links to the analyzed IBM Redbooks:

IBM z17 Technical Introduction

IBM z17 Technical Guide

IBM Z Connectivity Handbook

 A glossary of key terms mentioned in the redbooks:

• Mainframe: A powerful computer used primarily by large organizations for critical applications, typically involving large amounts of data processing such as census, industry and consumer statistics, enterprise resource planning, and large-scale transaction processing.
• Parallel Sysplex: A clustering technology for IBM Z mainframes that allows multiple systems to operate as a single logical system for increased availability and scalability.
• GDPS (Geographically Dispersed Parallel Sysplex): A configuration that extends a parallel sysplex across geographically separate sites for disaster recovery and continuous availability.
• N-minus-2 Rule: A compatibility guideline in IBM Z sysplex environments stating that a new mainframe model can typically work with the two preceding generations of mainframe models.
• Coupling Facility (CF): A specialized logical partition or dedicated machine used in a parallel sysplex environment to provide high-speed, shared data access and coordination between the participating systems.
• Integrated Coupling Adapter (ICA SR 2.0): A short-range coupling technology for connecting mainframe systems within a data center, offering low latency and high bandwidth.
• Coupling Express 3 Long Reach (CX3 LR): A long-range coupling technology used to connect mainframe systems located in different data centers, enabling geographically dispersed sysplex configurations.
• PCIe Drawer: A physical component in the IBM Z17 system that houses Peripheral Component Interconnect Express (PCIe) cards, including those used for Coupling Express long-reach connections.
• DWDM (Dense Wavelength Division Multiplexing): An optical fiber multiplexing technology that transmits multiple data signals simultaneously on different wavelengths of light over a single fiber, increasing bandwidth and transmission distance.
• CPC Drawer: A Central Processor Complex drawer, which is a physical component in the IBM Z17 system that contains the processors and memory.
• IBM Telum 2 Processor: The central processing unit designed by IBM that powers the Z17 mainframe.
• Core: An individual processing unit within a multi-core processor. The Telum 2 processor has eight high-performance cores per chip.
• Clock Rate: The speed at which a processor executes instructions, typically measured in gigahertz (GHz). The Telum 2 processor runs at 5.5 GHz.
• Cache Memory: A small, high-speed memory used by the processor to store frequently accessed data, reducing the time needed to retrieve information from main memory.
• Level 2 Cache (L2): A secondary level of cache memory that is larger and slower than Level 1 cache but still faster than main memory. Each Telum 2 core has 36 MB of L2 cache.
• Virtual Level 3 Cache (L3): A larger, shared cache pool that serves the processor cores in a multi-core module, further reducing the need to access main memory. The Telum 2 has 360 MB of virtual L3 cache per dual-chip module.
• Onchip Ring Interconnect: A high-bandwidth communication pathway integrated directly onto the processor chip that connects the cores, cache, and other components.
• PU Chip (Processor Unit Chip): A physical chip containing multiple processor cores. Each dual-chip module in the Telum 2 has two PU chips.
• Transistor: A fundamental building block of modern electronic devices, acting as a switch or amplifier. The high transistor count indicates the complexity and processing power of the chip.
• Memory Controller Unit: A component that manages the flow of data between the processor and main memory. The Z17 can accommodate up to 24 memory controller units.
• Main Memory: The primary storage area in a computer where data and instructions are held for processing. In the Z17, it can total up to 64 TB across all CPC drawers.
• LPAR (Logical Partition): A division of a mainframe’s resources (processors, memory, I/O) into multiple virtual machines, each capable of running its own operating system and applications independently.